Advanced technology for storage and networking applications.
General Description
The PowerPC 440SP Processor, a member of the PPC440 embedded processor family, offers exceptional performance, high bandwidth, design flexibility, and robust features geared to demanding embedded storage and networking applications. It features PowerPC Book E Enhanced Architecture, delivers speeds of up to 667MHz, and executes up to two instructions per cycle. With three PCI-X version 2.0 interfaces, an on-chip double data rate (DDR I/DDR II) SDRAM controller, I2O messaging unit, XOR accelerator unit, and a rich peripheral mix, the PowerPC 440SP processor is ideally suited for RAID controllers and storage area networking (SAN) equipment.
The PowerPC 440SP processor is built with IBM's advanced 0.13-micron CMOS copper process technology and an innovative design provide low power dissipation and a small footprint. Application code compatibility with other PowerPC processors enables manufacturers to bring products to market quickly to satisfy changing needs. High integration with robust peripheral support can further simplify board design and help provide cost-effective solutions.
Highlights
Delivers 533MHz to 667MHz performance for embedded I/O processor designs
32-bit implementation of the Book E Enhanced PowerPC® Architecture
Superscalar PowerPC 440 core with 32K-I/32K-D L1 caches and high-speed IBM CoreConnect™ bus technology
256K L2 cache with parity protection – may also be used as on-chip SRAM
High-speed Processor Local Bus (PLB) with 2-way crossbar, supports 10.4GB/sec. peak bandwidth
PCI-X v2.0 DDR compatible (266MHz) bridge with two (2) 64-bit and one (1) 32-bit PCI-X interfaces
Dual-ported 32/64-bit SDRAM memory controller, interfaced to both PLB slave segments, supporting 166/333MHz DDR I and 333/667MHz DDR II
Built-in XOR function for parity generation and checking - offers one-channel DMA capability
Integrated I2O messaging with two-channel DMA controller
State-of-the-art peripherals including 10/100/1000 Ethernet MAC, UARTs, IIC
Offers low power dissipation and small form factor for high-density, power-conscious applications
Provides application code compatibility with other PowerPC processors
Features
PowerPC 440 Core
533 to 667MHz
1,334 DMIPS @ 667MHz
32K/32K I-cache/D-cache with parity protection
Dual-issue, superscalar, 7-stage pipeline
Book E Architecture, 32-bit implementation
Memory management unit
L1 Cache Array and Tag Parity
Option to enable semi-recoverable or fully recoverable modes
256KB L2 Packet/Code-store on-chip memory
Configurable as either L2 cache or packet/code store memory
L2 cache: Unified, 4-way set-associative
Packet/code store: PLB-attached, accessible by 440 core and peripheral cores
Parity support on SRAM
CoreConnect
Up to 166MHz CoreConnect Processor Local Bus (128-bit PLB), two-way crossbar structure
64 bits addressing allowing 40GB of PCI memory space
Up to 83MHz CoreConnect architecture On-chip Peripheral Bus (32-bit OPB)
32/64-bit DDR I/DDR II SDRAM Controller, for DDR166/333 and DDR333/667 operation
SDRAM Controller configurable as 64-bit or 32-bit data width
Up to two 2GB logical banks, for a total of 4GB
Optional 8-bit ECC protection
Sustainable 2.6GBps peak band
width at DDR333 or 5.3GBps at DDR667
Data Saver (sustaining refresh during soft resets)
PCI-X 3.3V Multiport Bridge
Three PCI-X version 2.0 interfaces, up to 133MHz / DDR266
64-bit primary (host) bus, 64-bit secondary (local) bus, and 32-bit secondary (local) bus
