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  PPC440GX Prozessoren
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 PPC440GX  PPC440  AMCC  PowerPC 440  800MHz  0  CBGA 552, FCPBGA 552
  

Advanced processing capability for high-performance embedded systems

General Description

The AMCC PowerPC 440GX processor offers the versatility and bandwidth required for today's demanding networking and storage applications. This highly integrated device delivers CPU performance of up to 800MHz and executes up to two instructions per cycle. A PCI-X interface that supports frequencies of up to 133MHz and an on-chip double data rate (DDR) SDRAM controller, supporting up to DDR333, further enhance processor capabilities. With embedded state-of-the-art peripheral cores, the 440GX processor is ideal for networking control plane applications, RAID controllers, iSCSI processing, and storage area networking (SAN) equipment.

I/O processing applications can benefit from the integrated messaging unit, designed to the I2O specification. This messaging unit improves system performance by enabling the 440GX processor to communicate via I2O messages with a host system on the PCI bus. This allows the processor to work as an intelligent I/O adapter controller.

The 256KB on-chip SRAM can be configured either as a performance-enhancing L2 cache, or as memory-mapped SRAM for low-latency access. Used as L2, the 256KB SRAM is a 4-way set-associative, unified data/instruction cache, which can benefit many applications. As memory-mapped SRAM, it has lower memory access latency than the SDRAM, offering quick access to crucial code or data. Software-controlled and with parity support, this memory is ideal for storing data packets, critical code segments, Ethernet or DMA descriptors, or other application-specific data. When configured as a memory-mapped region, this SRAM is accessible from any PLB master, which can further improve application performance.

Highlights

  • Delivers 500 to 800MHz performance - with low power in a small form factor
  • Provides 256KB on-chip SRAM, configurable as an L2 cache or as packet/code-store memory for low-latency access
  • Integrates state-of-the-art peripherals, such as PCI-X and DDR SDRAM
  • Offers four Ethernet interfaces, including two 10/100/1Gb MACs with jumbo frame support, for increased bandwidth and connectivity
  • Embeds TCP/IP Acceleration Hardware (TAH), freeing CPU core cycles for other application demands
  • Includes a messaging unit that facilitates communications over the PCI, for increased application performance
  • Ensures PowerPC application code compatibility, as well as offering enhanced data integrity through processor parity

Features

  • The PowerPC 440GX processor provides the ability to develop high-performance, high-functionality networking and storage applications:
  • PowerPC 440 Core
    • 500 to 800MHz, 2.0 DMIPS/MHz
    • 32K/32K I-cache/D-cache with parity (tags and arrays)
    • Dual-issue, superscalar, 7-stage pipeline
    • Book E architecture, 32-bit implementation
    • Memory management unit with parity
  • CoreConnect
    • Up to 166MHz CoreConnect Processor Local Bus (128-bit PLB) with separate read and write databases
    • Up to 83MHz CoreConnect On- chip Peripheral Bus (32-bit OPB)
    • 36-bit address, 64GB memory map
  • 32/64-bit DDR200-DDR333 SDRAM Controller
    • Up to four 512MB logical banks, for a total of 2GB
    • Optional 8-bit ECC protection
    • Sustainable 2.6GBps peak bandwidth at DDR333
  • 32/64-bit PCI-X Interface, up to 133MHz
    • 800 MBps sustained bandwidth, 1.1GBps peak bandwidth
    • Support for PCI v2.3, up to 66MHz
    • Ability to boot from PCI-X bus memory
  • Messaging Unit (I2O specification) that facilitates communication between 440 core and PCI-X
  • 256KB on-chip SRAM
    • Configurable as either L2 cache or packet/code store memory
    • L2 cache: Unified, 4-way set- associative
    • Packet/code store: PLB-attached, accessible by 440 core and peripheral cores
    • Parity support on SRAM
  • External Bus Control (EBC) Interface
    • Up to 83MHz, 32-bit address bus, 32-bit data bus
    • Support for up to 8 ROM, RAM, or slave peripheral I/O devices
    • 4-channel DMA support for external peripherals
    • External bus master controller for access to internal peripherals
  • DMA Controller
    • Four independent channels, supporting internal and external peripherals
    • Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers
    • Scatter/gather capability
    • 128-byte buffer with programmable thresholds




 
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