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  PPC405CR Prozessoren
  Auflisten & Vergleichen        
  Bauteil Familie Hersteller Core Variante Freq. Flash/ROM Package
 PPC405CR  PPC405  AMCC  PowerPC 405  266MHz  0  E-PBGA 316
  

Highlights

  • Offers high performance and value for a wide variety of embedded applications, including wired communications, data storage and pervasive computing devices
  • Application code compatible with all other PowerPC® processors
  • Built with reusable core-based design principles with many functions pre-verified in silicon
  • Utilizes 64-bit CoreConnect™ bus architecture at up to 133MHz, providing high-speed on-chip performance with low latencies
  • Offers an effective functional and performance upgrade to designs based on the PowerPC 403GCX embedded processor
  • Implements innovative CodePack™ code compression, improving instruction code density and reducing overall system cost
  • Low power consumption for thermally sensitive environments
PowerPC 405B3 embedded core
  • 133, 200 or 266MHz CPU core
  • Memory Management Unit
  • 16KB instruction and 8KB data caches
  • Multiply-Accumulate (MAC) function, including fast multiply unit
  • 5-stage pipeline
  • Timers
  • JTAG and non-invasive trace debug logic
SDRAM controller
  • 4 chip selects, 4MB to 256MB per bank
  • PC100 (200MHz) and PC133 (266MHz) compliant
  • Supports dual- and quad-bank SDRAMs with 11x8 to 13x11 addressing
  • Programmable address mapping and timing
  • Separate 32-byte read and 128-byte write buffers
  • Power management (self-refresh)
  • 32-bit external data bus width
  • ECC option
External peripheral controller
  • Supports ROM, EPROM, SRAM, Flash and slave peripheral I/O devices
  • 8 banks
  • Burst and non-burst devices
  • 8-, 16-, 32-bit external data bus width
  • Latch data on ready, synchronous or asynchronous
  • Parity option
  • Programmable address mapping
CodePack decompression
  • Instructions stored in memory in compressed format
  • Improves code density up to 40%
  • No loss in instruction set capability
External bus master controller
  • Allows external masters to access SDRAM
DMA Controller
  • 4 independent channels
  • 8-, 16-, 32-bit peripheral support
  • Supports buffered memory-to-peripheral, peripheral-to-memory and memory-to-memory transfers
  • Scatter/gather capability with command/ data chaining
  • 32-byte data buffer
  • Supports transfers between SDRAM, PCI, internal UARTs, and devices on the external peripheral bus
Other On-Chip Peripherals
  • 2 serial ports (16550), 9-pin and 4-pin
  • Master and slave IIC controller, compliant with Phillips I2C spec
  • Up to 23 general purpose I/Os
  • Interrupt controller including up to 12 external interrupts




 
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