The Infineon C166 Family of 16-bit microcontrollers offers devices that provide various
levels of peripheral performance and programmability utilizing the powerful C166®S V1 core. This allows you to equip each specific application with the microcontroller that fits best to the required functionality and performance.
Still the Infineon family concept provides an easy path to upgrade existing applications
or to climb the next level of performance in order to realize a subsequent more
sophisticated design. Two major characteristics enable this upgrade path to save and
reuse almost all of the engineering efforts that have been made for previous designs:
• All family members are based on the same basic architecture
• All family members execute the same instructions
(except for upgrades for new members)
The fact that all members execute basically the same instructions saves know-how with
respect to the understanding of the controller itself and also with respect to the used tools
(assembler, disassembler, compiler, etc.).
This instruction set manual provides an easy and direct access to the instructions of the
Infineon 16-bit microcontrollers by listing them according to different criteria, and also
unloads the technical manuals for the different devices from redundant information.
This manual also describes the different addressing mechanisms and the relation
between the logical addresses used in a program and the resulting physical addresses.
There is also information provided to calculate the execution time for specific instructions
depending on the used address locations and also specific exceptions to the standard
rules.
The C166®S V1 is an enhanced member of the Infineon family of full featured 16-bit single-chip microcontrollers. It combines high CPU performance with high peripheral functionality. Several key features contribute to the high performance of the C166®S V1 (the indicated timings refer to a CPU clock of 100 MHz):

High Performance 16-Bit CPU With Four-Stage Pipeline

• 20 ns minimum instruction cycle time, with most instructions executed in 1 cycle
• 100 ns multiplication (16-bit *16-bit), 200 ns division (32-bit/16-bit)
• Multiple high bandwidth internal data buses
• Register based design with multiple variable register banks
• Single cycle context switching support
• 16 MBytes linear address space for code and data (von Neumann architecture)
• System stack cache support with automatic stack overflow/underflow detection
  

• Bit, byte, and word data types
• Flexible and efficient addressing modes for high code density
• Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags
• Hardware traps to identify exception conditions during runtime
• HLL support for semaphore operations and efficient data
• access

• Multiplexed or demultiplexed bus configurations
• Segmentation capability and chip select signal generation
• 8-bit or 16-bit data bus
• Bus cycle characteristics selectable for five programmable address areas

• Up to 112 interrupt nodes with separate interrupt vectors
• 16 priority levels and 4(8) group levels

• Interrupt driven single cycle data transfer
• Transfer count option (std. CPU interrupt after programmable number of PEC transfers)
• Long Transfer Counter
• Channel Linking
• Eliminates overhead of saving and restoring system state for interrupt requests