Instruction set upward compatible with SuperH RISC Family:
 • Upward compatible with SH-1 and SH-2 Family of devices
• Compact 16/32-bit instruction code
• Flexible addressing modes.

Integrated SH-2A CPU engine and FPU optimized for performance, low power and cost:
• Improved performance
– 1.5x performance compared to
SH-2 architecture
• Better code density
– 75% code-size reduction compared
to SH-2 core
• Real-time control
– 6-cycle interrupt-response time
• Floating Point Unit (FPU):
– 1.4 GFlops performance

Easier to program; simplified product development:
• Multitasking instead of
multiprocessing
• Eliminates inter-processor
communication
• Single hardware/software
design environment