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Home » Freescale ColdFire
Freescale ColdFire
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ColdFire Architecture
Implementation Methodology Designed for Reuse - All cores are 100% fully synthesizable
- Parameterizable - all options exist within a single design description
- Configurable
- Generic local-memory controllers support a range of sizes
- Choose size using compiled
memory arrays
- Hierarchical architecture
- Multiple buses provide layers
of bandwidth + modularity
- Standard internal bus structure provides simple interface
- Design-for-Test
- Muxed D-FF rising-edge clocked design
- ATPG scan vectors
for stuck-at, speed testing
- BIST test methodology for memories
- Deployment focused on soft macro RTL + support of hard macros
V2 ColdFire Core:Single-Issue
The ColdFire2/2M is part of a semicustom,
standard-cell based design program. High-volume manufacturers can create their own integrated
microprocessor containing a core processor (such as the ColdFire2/2M) and their own ...
V3 ColdFire
Core:Single-Issue + Pipelined Local Bus
The ColdFire 3 core delivers enhancements including a refined instruction prefetch
pipeline, branch prediction capabilities, and higher frequencies of operation. These improvements allow
the core to provide up to 300% ...
V4 ColdFire Core:Limited Superscalar
The next-generation ColdFire® microarchitecture
provides a 2.8x performance improvement when compared with the ColdFire 3 core over a broad range of
applications. Improved microarchitecture for higher performance: greater than 200 Dhrystone ...
V4e ColdFire Core:Limited Superscalar
The V4e is designed to provide hardware support for on-chip multiprocessing for systems requiring
intensive numeric processing capabilities beyond that provided by a single processor. Designs
implemented in 0.18 micron ...
V5 ColdFire Core:Full Superscalar
Performance Targets: 1.3x - 1.4x V4{e} core
performance in same process technology; 2x V4{e} system-level performance in next-generation process
Maintain attributes of family heritage ... |
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